(1) Field of the Invention
The present invention relates to a bit synchronization circuit and, more particularly, to a bit synchronization circuit suitable for converting high-speed burst data signals received from a transmission line into data signals synchronized with an internal reference clock.
(2) Description of Related Art
As a transmission system that relays burst signals transmitted from multiple terminals, a Passive Optical Network (PON) system is known. The PON system is an optical transmission system having a topology, as shown in FIG. 2, wherein each of optical fibers 11 (11-1 to 11-m) connected to a central office side apparatus (Optical Line Terminal: OLT) 1A diverges, with an optical splitter (star coupler) 12 located on each optical fiber, into branch optical fibers 13 (13-1 to 13-n) for connecting with subscriber connection apparatuses (Optical Network Units: ONUs) 10 (10-1 to 10-n).
To each subscriber connection apparatus 10, at least one subscriber terminal (not shown) is connected and data transmitted from each subscriber terminal is forwarded via the central office side apparatus 1A to a core network 14. The core network 14 may be either the Internet to which various servers to be accessed by subscriber terminals are connected or a transit network for connecting a plurality of central office side apparatuses (1A, 1B, . . . ). The PON can provide an economical Fiber to the Home (FTTH) access network, because it enables multiple subscribers to share an optical fiber transmission line 11 and a low cost star coupler 12 which is easy to maintain can be used as a device to diverge the optical fiber transmission line 11 into a plurality of branch optical fibers 13.
The PON is classified, for example, into a Broadband PON (B-PON) that transmits data in the form of ATM cells, a Gigabit PON (G-PON) that enables high-speed data transfer in the order of gigabits per second, and a Giga-Ethernet PON (GE-PON) suitable for Ethernet services.
In the PON system, upstream data frames transmitted from the subscriber connection apparatus 10 to branch optical fibers 13 are time division multiplexed on the optical fiber 11. Each upstream data frame 200 is comprised of a preamble 210 and payload 220, as shown in FIG. 3, and the payload 220 includes data packets transmitted from each subscriber terminal.
To avoid collision of data transmitted from a plurality of subscriber connection apparatuses on the optical fiber 11, each subscriber connection apparatus 10 transmits its upstream data frame 200 within a time zone specified from the central office side apparatus 1A. In consequence, a plurality of upstream data frames are time division multiplexed on the optical fiber 11, locating no-signal intervals (guard time) between frames, and are input as burst data to the central office side apparatus 1A.
On the other hand, downstream data transmission from the central office side apparatus 1A to the subscriber connection apparatuses 10-1 to 10-n is performed in a broadcast communication manner. In a downstream data frame transmitted from the central office side apparatus 1A to an optical fiber 11-1, a plurality of data packets with different destination addresses are arranged continuously without locating no-signal intervals between them. Each of the downstream data frames is multicasted to the branch optical fibers 13-1 to 13-n by the optical coupler. Each subscriber connection apparatus 10 selectively takes in only a packet addressed thereto, by determining the destination address of each packet included in a received frame, and forwards the packet to the destination subscriber terminal.
Each downstream data frame is transmitted at a frequency f0 synchronized with an internal reference clock of the central office side apparatus 1A or at a multiplier frequency of f0. Each subscriber connection apparatus 10 extracts the basic clock from the downstream frame and transmits respective upstream data frames at the frequency f0 synchronized with the internal reference clock. That is, the frequency of upstream burst data received by the central office side apparatus 1A is synchronous with the internal reference clock.
In the PON system, however, when each upstream data frame (burst data) arrives at the central office side apparatus 1A, a phase difference relative to the above internal reference clock varies depending on the subscriber connection apparatus, because the branch fibers 13-1 to 13-n diverging from the optical splitter 12 have different lengths. Therefore, the central office side apparatus 1A has to perform bit synchronization for each burst data after performing optical-to-electrical conversion on burst data received from the optical fiber 11.
FIG. 4 shows a model of burst data which is input to a bit synchronization circuit (timing extraction circuit) in the central office side apparatus 1A. Each burst data includes a preamble 210 comprising of, for example, a sequence of alternating “1” and “0” bits preceding a payload 220, as described for FIG. 3. The central office side apparatus 1A has to establish bit synchronization for each burst data during a period of receiving the preamble 210. On the other hand, data effective for a subscriber connection apparatus is carried with payload 220 and it is desired to make the preamble 210 as short as possible in order to improve transmission efficiency in a PON section.
The central office side apparatus 1A also needs an Automatic Threshold Control (ATC) function to detect an input signal level for each burst data and to automatically change a threshold Th for discriminating high and low levels of the input signal at a stage previous to the bit synchronization circuit. This is because the amount of attenuation of the burst data signal during transmission on an optical fiber varies depending on the length of the optical fiber through which the burst data passes. Since the ATC generally determines the threshold Th by detecting the peak level of the input signal, it is known that, when a noise component such as spike noise is superimposed on burst data, the threshold Th is set at a higher level than an ideal level and a pulse width distortion occurs, as denoted by W (L) and W (H), in the input signal of the bit synchronization circuit.
In the G-PON having a transmission capacity in the order of gigabits per second, there is a possibility that long burst data, for example, with a duration of 125 μs, is input to the bit synchronization circuit of the central office side apparatus 1A, because each subscriber connection apparatus 10 is allowed to transmit variable length burst data. For long burst data, it is necessary to take into consideration that phase variation will occur due to jitter/wander during burst data reception or due to out of frequency synchronization between the internal reference clock and received burst data. Therefore, a PON system which allows variable length burst data transmission requires a bit synchronization circuit that has a function of tracking a phase variation during a payload receiving period in addition to a function of determining an initial phase during a preamble receiving period.
To solve the above-described problem, for example, Japanese Unexamined Patent Publication No. 2005-012305 (patent document 1) proposes a bit synchronization circuit of an optimum phase data selection type, which is comprised of, as shown in FIG. 5, a multi-phase data sampling unit 50 for converting received burst data into N-phase data streams, a phase determining unit 51 for generating a control signal indicating an optimum phase data stream, an output data selector 55 for selecting an optimum phase data stream indicated by the control signal from among the N-phase data streams, a missing data supplying unit 56 for supplying data that is missed when the optimum phase data is switched from one to another, and an output data synchronizing unit 60 for converting the optimum phase data stream supplied from the output data selector 55 into a data stream synchronized with the reference clock. The phase determining unit 51 repeatedly performs an operation of detecting an optimum phase data stream during a period of receiving the same burst data. When the optimum phase changes, the output data selector 55 dynamically switches to the optimum phase data stream to be supplied to the output data synchronizing unit 60.
Here, the multi-phase data sampling unit 50 generates N-phase data streams by latching received data with N-phase clocks generated by delaying the reference clock CL and reading out the latched N-phase data in synchronization with the reference clock CL. The phase determining unit 51 generates a switching control signal SC and a data stream correction signal SP, based on an optimum phase determined from signal change points of received data and a mask signal M generated by a mask signal generator 54. The switching control signal SC is supplied to the output data selector 55 and the data stream correction signal SP is supplied to a data transfer control unit in the output data synchronizing unit 60. The output data selector 55 selects an optimum phase data stream D1 from among N-phase data streams output from the multi-phase data sampling unit 50 in accordance with the switching control signal SC and supplies the data stream to data storage 57.
As described, for example, in Japanese Unexamined Patent Publication No. H9 (1997)-36849 (patent document 2), the phase determining unit 51 can select, by performing dual edge detection for detecting rising and falling pulse edges, a data stream having the greatest phase margins at both rising and falling edges of a pulse in comparison to the internal reference clock from among N-phase data, even if a pulse width distortion occurs. In the above patent document 1, detection of signal change points and determination of the optimum phase are performed for the entire length of received burst data and data missing or duplication, which may occur when the optimum data stream is switched to another data stream beyond the boundary of a clock cycle, is compensated by the missing data supplying unit 56 and the data transfer control unit 58.
However, the bit synchronization circuit described in the above patent document 1 intends to realize, with a single circuit, both the function of pulling into synchronization at the initial stage of burst data reception which starts in a state where a signal phase is unpredictable at all and the function of tracking a relatively moderate phase variation occurring after the initial phase is established, so that this circuit involves following problems.
Specifically, in order to rapidly pull the received burst data whose phase is unknown into synchronization, the phase determining unit 51 determines an optimum phase data stream by dual edge detection and supplies the result to the output data selector 55, thereby to dynamically or discretely switch over among multi-phase data. However, dynamic switching of output data to another phase data stream in accordance with the result of optimum phase data determination is a deviation from the intended purpose of the operation for the phase tracking operation performed after the initial phase is established. That is, in the above prior art, even if an error occurs in determining optimum phase data stream by the phase determining unit 51 due to, for example, noise or the like, the output data selector 55 instantaneously switches the optimum data stream from the current phase to another phase, jumping over multiple phases. As a result, continuity of output data is lost and contrivance is needed for compensating data missing or duplication.
In the above prior art, because a dual edge detection circuit and an operation circuit for optimum phase determination in the phase determining unit 51 are driven during the entire length of each burst data input, these circuits continue to consume power as long as burst data is received. Since the operation for optimum phase determination adaptive to a pulse width distortion has been completed within the preamble receiving period, it is meaningless to perform the operation for optimum phase determination based on the dual edge detection even for a period of receiving a payload in which a sequence of alternating “0” and “1” bits is not ensured. As a result, power is consumed uselessly in the phase determining unit 51.